1. Field of the Invention
The present invention relates to methods of designing low-power semiconductor integrated circuits. More specifically, the present invention relates to a method of designing a low-power semiconductor integrated circuit by changing the circuit layout results obtained through a top-down design methodology.
2. Description of the Background Art
In recent years, most logic LSIs are designed by using a top-down design methodology. The top-down design methodology typically includes a function design process, a logic synthesis process, and an automatic layout process. In the function design process, the designer uses a Hardware Description Language (HDL) to functionally describe a circuit to be designed. In the logic synthesis process, the functionally-described circuit is converted to circuit data at the gate level. In the automatic layout process, the designer uses an automatic layout tool to obtain layout results (results obtained by arranging cells included in the circuit, wiring between cells, etc.) based on the circuit data at the gate level. The obtained layout results are subjected to a timing verification process, a layout verification process, and other verification processes. By using the layout results after these verification processes, the actual device is manufactured.
Recently, an improvement in circuit integration level and an increase in circuit operation frequency have increased the complexity of the circuit design. Accordingly, it is extremely difficult to quickly complete the processes from the logic synthesis process to the automatic layout process. For this reason, there have been developed a large number of design tools, including a logic synthesis tool and an automatic layout tool, with the principle emphasis on quick completion of the processes rather than on the optimization of the circuit size or the chip size. In such design tools, quickly achieving timings indispensable for the operation of the circuit is highly valued. Therefore, circuits tend to have a large design margin. Such circuits with a large design margin, however, require a large amount of power consumption during operation. In order to reduce the power consumption of the circuit, therefore, reducing an excessive design margin at the circuit designing stage is crucial.
Examples of a scheme of reducing an excessive design margin from the circuit designed by using a top-down design methodology are a scheme of calculating the power consumption by using a circuit simulator and selecting an optimum cell (by using a device disclosed in Japanese Patent Laid-Open Publication No. 5-205006 (1993-205006), for example), a scheme of detecting a changeable cell in a circuit (refer to Japanese Patent Laid-Open Publication No. 11-330252(1999-330252), for example), and a scheme of designing a circuit with a limited function by using a design methodology specifically tailored to low power consumption.
FIG. 19 is a process chart of a low-power design scheme using a circuit simulator. The method illustrated in FIG. 19 includes a series of processes including a function design process S901, a logic synthesis process S902, an automatic layout process S903, a timing verification process S904, a layout verification process S907, and a device manufacturing process S908, together with a power consumption simulation process S905 and a circuit modification process S906. In the power consumption simulation process S905, power consumption of a circuit is calculated by using a circuit simulator based on layout results subjected to timing verification. If the calculated power consumption of the circuit exceeds a desired value, the circuit is modified in the circuit modification process S906. Then, in accordance with the degree of modification, the processes starting from the logic synthesis process S902, the automatic layout process S903, or the timing verification process S904 are performed again.
However, the above conventional low-power design schemes have the following problems. That is, in the above-stated scheme of calculating the power consumption by using a circuit simulator and selecting an optimum cell, a cell of the lowest power consumption is selected through repetitive calculation, thereby requiring an enormous amount of processing time and a long development period. Moreover, by merely performing optimum cell selection, a reducible amount of power consumption is limited. In the above-stated scheme of detecting a changeable cell, no specific measure for achieving this scheme exists so far, and therefore there has been no prospect for putting this scheme into practical use. Moreover, in the above-stated scheme of designing a circuit with a limited function, the operation of a circuit whose specifications are later determined depending on the application to be employed cannot be determined at an early stage in designing. Therefore, this scheme is not effective, either.
After all, in order to reduce power consumption of the circuit, it would be most effective to employ a scheme of reducing a design margin from final design data obtained immediately before a manufacturing process. However, no such scheme effectively achieving quick reduction in the power consumption of the circuit based on the final design data has yet been known. Therefore, currently employed in an actual development process is either one of a scheme of deleting the design margin through trial and error at the cost of the developing period and a scheme of manufacturing a circuit with its design margin untouched at the cost of power consumption.